EmbeddedPQC：超小型格子暗号ライブラリ、RISC-V/Cortex-M最適化コア、RTOSネイティブ統合

EmbeddedPQCは、32ビットARM Cortex-M、RISC-V、車載マイクロコントローラ向けに、超小型で固定時間実行（Constant-time）の格子暗号実装を開発し、極小メモリ容量のエッジセンサに耐量子セキュリティを提供します。

EmbeddedPQC システムアーキテクチャ

Core cryptographic topology and protocol interaction of embeddedpqc.com

Central System: Embedded Core - Cortex-M4 / RISC-V

Cryptographic Nodes

  • In-Place NTT
  • Stack Squeeze
  • Flash DMA
  • True RNG
  • SecOC Node

Architectural Layers & Protocols

  • In-Place Polynomial Transform (NTT) (Optimized Cooley-Tukey & Gentleman-Sande Butterfly Networks): Performing fast modular polynomial multiplication within a single preallocated buffer
  • Flash-Resident Streaming Keccak (SHAKE-256) (Chunked State Absorbing and Squeezing): Streaming public matrix A generation directly into NTT computation without storing full matrices in RAM
  • Hardware Acceleration & Crypto Extensions (ARM Cortex-M55 / M85 Helium Vector Extensions & RISC-V Vector (RVV)): Accelerating vector operations while maintaining strict constant-time branchless execution
  • Automotive & Industrial Bus Layer (AUTOSAR SecOC & CAN FD Cryptographic Framing): Injecting truncated post-quantum MACs into 64-byte CAN FD frames without breaking bus latency

Key Metrics: <8 KB (Peak SRAM Stack Usage) | ARM M4/M33 (Target Architecture) | RISC-V Zk (Crypto Extension Support) | Zero-Leak (Side-Channel Timing Proof)

エッジシリコンにポスト量子保護をもたらす

Connected vehicles, smart meters, and industrial IoT sensors often operate with less than 64KB of RAM and cannot accommodate memory-heavy cryptographic implementations. EmbeddedPQC optimizes lattice mathematics for constrained microarchitectures.

Core Engineering Areas

Technical Articles

Related Cluster Architecture Specifications