EmbeddedPQC: Librerías de Retículos Ultracompactas, Núcleos RISC-V/Cortex-M e Integración RTOS

EmbeddedPQC diseña implementaciones de criptografía de retículos ultracompactas y de tiempo constante para microcontroladores ARM Cortex-M de 32 bits, RISC-V y de automoción, habilitando seguridad cuántica en sensores perimetrales con huella mínima de memoria.

EmbeddedPQC System Architecture

Core cryptographic topology and protocol interaction of embeddedpqc.com

Central System: Embedded Core - Cortex-M4 / RISC-V

Cryptographic Nodes

  • In-Place NTT
  • Stack Squeeze
  • Flash DMA
  • True RNG
  • SecOC Node

Architectural Layers & Protocols

  • In-Place Polynomial Transform (NTT) (Optimized Cooley-Tukey & Gentleman-Sande Butterfly Networks): Performing fast modular polynomial multiplication within a single preallocated buffer
  • Flash-Resident Streaming Keccak (SHAKE-256) (Chunked State Absorbing and Squeezing): Streaming public matrix A generation directly into NTT computation without storing full matrices in RAM
  • Hardware Acceleration & Crypto Extensions (ARM Cortex-M55 / M85 Helium Vector Extensions & RISC-V Vector (RVV)): Accelerating vector operations while maintaining strict constant-time branchless execution
  • Automotive & Industrial Bus Layer (AUTOSAR SecOC & CAN FD Cryptographic Framing): Injecting truncated post-quantum MACs into 64-byte CAN FD frames without breaking bus latency

Key Metrics: <8 KB (Peak SRAM Stack Usage) | ARM M4/M33 (Target Architecture) | RISC-V Zk (Crypto Extension Support) | Zero-Leak (Side-Channel Timing Proof)

Llevando la Protección Poscuántica al Silicio de Borde

Connected vehicles, smart meters, and industrial IoT sensors often operate with less than 64KB of RAM and cannot accommodate memory-heavy cryptographic implementations. EmbeddedPQC optimizes lattice mathematics for constrained microarchitectures.

Core Engineering Areas

Technical Articles

Related Cluster Architecture Specifications